diningyo

advanced-computer-organization

zoom

🔍 Zoomable Waveform viewer for the Web

sv2chisel

(System)Verilog to Chisel translator

chisel-book

Digital Design with Chisel

tnoc

Network on Chip Implementation written in SytemVerilog

kami

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

vcd2step

Converts a VCD file to a Chisel tester input file

berkeley-softfloat-3

SoftFloat release 3

yosys

Yosys Open SYnthesis Suite

berkeley-hardfloat

sha3

gemmini-rocc-tests

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

hammer

Hammer: Highly Agile Masks Made Effortlessly from RTL

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

chisel-coverage

A coverage library for Chisel designs

chisel-cheatsheet

Chisel Cheatsheet

firrtl-interpreter

A scala based simulator for circuits described by a LoFirrtl file

risc-v

RISC-VのCPU作った

svls-vscode

SystemVerilog language server client for Visual Studio Code

svlint

SystemVerilog linter

sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

svls

SystemVerilog language server

biblio_doc

tinysixel

A tiny header-only C++ library for Sixel.

firechip

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-newlib

RISC-V port of newlib

riscv-rust-toolchain

RISCV Rust Toolchain