dimkatsi91 / VHDL_Lab

VHDL Lab Exercises from simple Combinational/Sequential circuits to a simple CPU design

VHDL Lab Exercises

MSc Course: "Design of Digital Systems with VHDL" (Lab Exercises)

MSc Title: "Electronics & Information Processing" @ University of Patras, Greece

Author: Dimos Katsimardos

Period: 2015 November - 2016 February

Description: VHDL lab exercises from simple behavioral and sequential circuits to a simple CPU design with hardwired and microprogrammed logic

Software/CAD: Altera Quartus 7.2

vhdl lab GitHub site

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• Simple Combinational Circuits

• Advanced Combinational Circuits

• Sequential Circuits

• Serial Adders/Subtractors

• Arithmetic & Logic Unit ( ALU )

• Up Down Presetable Counter - Universal Shift Register - Combinational Shift Circuit

• A very simple CPU