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alexforencich
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verilog-wishbone
Verilog wishbone components
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alexforencich/verilog-wishbone Issues
grant_valid is undefined in module wb_arbiter_2
Updated
a year ago
wb_async_reg: stb master unasserted pulse not registering
Updated
2 years ago
wb_async_reg: limit on clock ratio?
Closed
2 years ago
import wb in twst_wb_ram.py
Updated
2 years ago
Generating waves
Updated
2 years ago