wb_async_reg: limit on clock ratio?
rdolbeau opened this issue · comments
Hello,
I'm using the wb_async_reg in my project [1], but occasionally I have timeouts issue. I'm trying to track down the problem and was wondering if the wb_async_reg component had a limit on the clock ratio between the slave clock & the master clock.
In my use case, they are quite different, bridging between a domain at usually 25 MHz (nominally between 16.67 and 25) and a domain commonly at usually 100 Mhz (sometimes a bit lower to help meet timings).
In the test bench, if I set the clocks to my extreme values:
--- a/tb/test_wb_async_reg.py
+++ b/tb/test_wb_async_reg.py
@@ -144,7 +144,7 @@ def bench():
wbs_cyc_o=wbs_cyc_o
)
- @always(delay(4))
+ @always(delay(30))
def wbm_clkgen():
wbm_clk.next = not wbm_clk
Then the test bench just hangs. It seems that the ack is not propagated.
It also hangs if I permute the clock, not sure why exactly.
I'm a hardware newbie so maybe I've overlooked the obvious, I apologize if that's the case.
Thanks in advance for any help & cordially