Ahmed Abdelazeem's repositories
Chameleon_SoC
AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
Introduction-to-System-on-Chip-Design-Online-Course
To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA platforms using standard hardware description and software programming languages
ASIC-Implementation-of-a-Cruise-Control-System-
This Paper presents a modified Cruise Control System application specific integrated circuit (ASIC) with speed feedback controller in motor drive. The proposed cruise Control ASIC not only decreases the ripple of hysteresis controller but also enhances the performance of motor controller. Verilog hardware description language (Verilog HDL) is used to implement the hardware architecture; and that an ASIC is fabricated in Nangate 45nm process with cell-based design method. Both switching and calculating delay times mainly contribute the ripples which degrade the control quality in motor drive. By using the predictive scheme, we not only improve the ripple issue of the traditional direct torque control technique, but also make the control system more stable by decreasing the time delay in hysteresis controller. According to the measured results, the proposed Cruise Control System ASIC performs with the coverage of 99.10 % and the fault coverage of 98.28 % at the operating frequency of 250 MHz, the supplied voltage of 1.2 V and the power consumption of 36.9976 uW.
Pipelined-FFT-IFFT-64-points
The USFFT64 User Manual contains description of the USFFT64 core architecture to explain its proper use. USFFT64 soft core is the unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 64 – complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.
Two-Stage-CMOS-Operational-Amplifier-Analysis-and-Design
-in this presented paper design and implementation of two stage operational amplifier operates at 2.9V to 3.7V power supply at 180nm CMOS technology. The proposed two stage op amp produces high gain. Design and simulations results are verified using CADENCE tool. This design has accomplished a high power supply rejection ratio (PSRR) greater than -80db and other performance parameters such as input common mode range (ICMR), common mode rejection ratio (CMRR) and slew rate is verified.
i3c-slave-design
MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
dsi-shield
Arduino MIPI DSI Shield
FPGA-I2C-Slave
A simple I2C slave in VHDL
EE-454-Portable-Ultrasound
The repository for our portable ultrasound and quickhull project.