Ahmed Abdelazeem's repositories
ASIC-Implementation-UART
This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from system clock. If we increase the baud rate, speed of serial data transmission increases. As the dividing factor decrease baud rate increases. in this paper we set the system clock frequency as 50MHz and time to transfer each data bit is 23.75ns with baud rate of 42.1 Mbps (dividing factor is 32). Due to increase in the baud rate the time taken to transfer the data decreases, so it is very useful for faster communication devices. Transmitter and Receiver blocks designed by algorithm state machine method simulated in ModelSim, synthesized in Design Compiler, and extracted in ICC in Nangate 45 nm CMOS cell library.
5-Stage-Pipeline-RISC-V-RV32I
The goal of this Project is to design a RISC-V processor with 5 pipeline stages. The version of the RISC-V processor supports only a limited subset of the whole RV32I instruction set, but in the design here reported all the standard instructions except ECALL, EBREAK, and FENCE are implemented.
Cordic-Algorithm-ASIC-chip
Verilog implementation of a Cordic Algorithm ASIC chip based on SMIC 180nm standard digital technology. Fulfill the conversion from Rectangular to Polar Coordinates for arbitrary coordinate on RTL level.
Difference-between-blocking-and-non-blocking-statements-in-Verilog
In case of Verilog, blocking and non-blocking statements are two methods to make use of combinational and sequential logic to implement the design.
Computer-architecture-and-organization
Computer architecture and organization
Microcontrollers-based-on-the-Arm-Cortex-M0
This example design is based on the Arm Cortex-M System Design Kit (CMSDK) reference design.
Static-Time-Analysis
Static Time Analysis
LIFO-and-FIFO-Data-Structures
In audio, we often use std::vector and arrays for holding data. It is a flexible data structure that allows random reads and writes. However, we may want to restrict the processing order. In this case, we may use other STL container classes or we may create data structures such as stacks and queues. Two common data structures in computer science are LIFO (last-in-first-out) and FIFO (first-in-first-out).
awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
e203_hbirdv2
The Ultra-Low Power RISC-V Core
gf180mcu-pdk
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
globalfoundries-pdk-ip-gf180mcu_fd_ip_sram
SRAM macros created for the GF180MCU provided by GlobalFoundries.
globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
7 track standard cells for GF180MCU provided by GlobalFoundries.
globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
9 track standard cells for GF180MCU provided by GlobalFoundries.
learn-regex
Learn regex the easy way
Open-CryptoNight-ASIC
Open source hardware implementation of classic CryptoNight
skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
TIGFET-10nm-PDK
An open source PDK using TIGFET 10nm devices.
tt03-xor-cipher
Verilog demo for Tiny Tapeout 03
riscv-formal
RISC-V Formal Verification Framework
UVMReference
Reference examples and short projects using UVM Methodology