abdelazeem201 / RTL-to-Gates-Synthesis-using-Synopsys-tools

For this assignment, you will become familiar with the VLSI tools you will use throughout this semester, learn how a design “flows” through the toolflow, and practice Verilog coding. Specifically, you will write an RTL model of a GCD circuit, synthesize and place and route the design, simulate at every stage, and analyze power.

For this assignment, you will become familiar with the VLSI tools you will use throughout this semester, learn how a design “flows” through the toolflow, and practice Chisel coding. Specifically, you will write an RTL model of a greatest common divisor (GCD) circuit, synthesize and place and route the design, simulate at every stage, and analyze power