Yosys Headquarters

yosys

Yosys Open SYnthesis Suite

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

nextpnr

nextpnr portable FPGA place and route tool

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

oss-cad-suite-build

Multi-platform nightly builds of open source digital design and verification tools

apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

prjtrellis

Documenting the Lattice ECP5 bit-stream format.

sby

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

fpga-toolchain

Multi-platform nightly builds of open source FPGA tools

riscv-formal

RISC-V Formal Verification Framework

mcy

Mutation Cover with Yosys (MCY)

nerv

Naive Educational RISC V processor

VlogHammer

A Verilog Synthesis Regression Test

eqy

Equivalence checking with Yosys

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

padring

A padring generator for ASICs

yosys-tests

Collection of test cases for Yosys

setup-oss-cad-suite

Set up your GitHub Actions workflow with a OSS CAD Suite

prjtrellis-db

Project Trellis database

sby-gui

GUI for SymbiYosys

scy

Sequence of Covers with Yosys

Sublime-Yosys

Yosys syntax highlighter for the Sublime Text 3 editor

nextpnr-tests

pyosys-tests

pyosys tests

yosyshq.github.io

www.yosyshq.net

mau

Modular Application Utilities

yosys-web

Yosys Web Page

yosys-manual-build

Yosys manual

.github

furo-ys

A clean customizable documentation theme for Sphinx