VLSIDA/OpenRAM Issues
Runtime
Updated 8Error in SRAM creation with banks
Updated 6Not generate certain module
Closed 1Power estimation seems too high
Updated 14Support for ASAP7 PDK
Closed 1Import custom file
Closed 3Importing a custom GDS file.
Closed 7multiports bitcell
Closed 1ROM >= 8k fails to build
Updated 3ROM dump + replace contents
UpdatedSupport for PROBE PDK
Updated 4LVS mismatch errors in SKY130 SRAM
Updated 1openram.py doesn't exist in any tree
Updated 1Feature request: PROM
Closed 1ROM generation tutorial/references
Updated 2Virtuoso Layout using freepdk45
Closed 2Support for IHP PDK
Updated 1Anaconda install problem
Closed 8the meaning of local_array_size
Closed 3