multiports bitcell
YWJ226 opened this issue · comments
Hi, I saw on the official website of OpenRAM that it supports generating multi-port devices, and the displayed bitcell structure supports at least three ports. However, when I tried to generate a three-port device, I found that the bank.py file only supports up to two ports. Could you please tell me how to modify it to generate a three-port bitcell, or are there any related documents available?
It can generate the netlist but the top level layout is not possible due to the arrangement of the ports. We assume one goes on the left/bottom and the other on the top/right.