Sanchit-20 / Ten_Bit_Multiplier

Designed 10 bit multiplier, implemented using structural and RTL level design, and the functionality of 10 bit adder is completely synchronous.

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Ten_Bit_Multiplier

Designed 10 bit multiplier, implemented using structural and RTL level design, and the functionality of 10 bit adder is completely synchronous.

About

Designed 10 bit multiplier, implemented using structural and RTL level design, and the functionality of 10 bit adder is completely synchronous.


Languages

Language:VHDL 100.0%