NickolayTernovoy

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

universal

Large collection of number systems providing custom arithmetic for mixed-precision algorithm development and optimization for AI, Machine Learning, Computer Vision, Signal Processing, CAE, EDA, control, optimization, estimation, and approximation.

gf180mcu-pdk

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

pyuvm

The UVM written in Python

caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

fpga_craft

A voxel game/Minecraft clone for the iCE40 UP5K FPGA

fpga-awesome-list

Полезные ресурсы по тематике FPGA / ПЛИС

APS

Методические материалы по разработке процессора архитектуры RISC-V

Altera-Cyclone-IV-board-V3.0

Documentation for Chinese ALTERA Cyclone IV EP4CE6 FPGA Development Board

chiselv

A RISC-V Core (RV32I) written in Chisel HDL

iCE40linux

Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker

SoftPosit.jl

A posit arithmetic emulator.

flexfloat

C library for the emulation of reduced-precision floating point types

Static-Timing-Analysis-Full-Course

Static Timing Analysis Full Course

PERCIVAL

Open-Source Posit RISC-V Core with Quire Capability

PDPU

PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications

jordi

gRPC TUI

Chisel-Training

yrv

Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

circular-queue-verilog

Implementation of a circular queue in hardware using verilog.

WaveGen

FlexRV32

The second implementation of RISC-V architecture, step-by-step.

playhdl

🪀 Tool to play with HDL (inspired by EdaPlayground)

Papers_STA

verilator_playground

LZC

Leading-Zero Counting (for FPU)

Risc-V

RISC-V CPU implementation

ObsidianVerificationTracker

yrv-plus

Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.