DmitryZlobec / yrv-plus

Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

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yrv

This RISC-V implementation is described in the book "Inside An Open-Source Processor" ISBN 978-3-89576-443-1

Added DE0 an DE0-CV suppurt Added GCC toolchain support

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Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

Apache License 2.0

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Language:Verilog 54.7%Language:C 29.2%Language:SystemVerilog 4.1%Language:Assembly 3.2%Language:Coq 3.0%Language:Shell 2.6%Language:Makefile 1.8%Language:Tcl 1.2%Language:Python 0.2%Language:Batchfile 0.1%