MukkeshGandhi09

lz4

Extremely Fast Compression algorithm

NyuziProcessor

GPGPU microprocessor architecture

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

projf-explore

Project F brings FPGAs to life with exciting open-source designs you can build on.

vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Physical-Design

Physical Design Flow from RTL to GDS using Opensource tools.

mixedsim

Hardware Design Tool - Mixed Signal Simulation with Verilog

fpgatools

Tools for FPGA development.

Viterbi-Decoder-in-Verilog

An efficient implementation of the Viterbi decoding algorithm in Verilog

FPU-IEEE-754

Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for floating point numbers

lzrw1-compression-core

This is the repository for a verilog implementation of a lzrw1 compression core

Image-Encryption-using-Chaotic-Synchronization

📖 ECPC23 - Analog Integrated Circuits Course Project

Digital-Signal-Processor-Design-in-FPGA