Mukesh Gandhi's repositories
Summer-Intern
Summer Intern
RISC-V-CPU
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
VLSI
RISC V core implementation using Verilog.
Language:Tcl000
MukkeshGandhi09
Spider R&D club of NITT
Tiruchirappalli
Organizations
