riscv / riscv-v-spec

Working draft of the proposed RISC-V V vector extension

https://jira.riscv.org/browse/RVG-122

riscv/riscv-v-spec Issues

example of vmv.v.* is inconsistent with the definition in spec-1.0.pdf?
Updated 4 months ago3
README should reflect that rvv has been ratified
Updated 4 months ago1
what's the vd of vcompress in case of vl =0
Closed 5 months ago5
Spec PDF does not have PDF TOC
Updated 5 months ago
Mask instruction tail elements behavior issue(while vl=0)
Closed 5 months ago2
wha
Closed 5 months ago
What is the destination value beyond the tail for compare instruction under tail agnostic?
Updated 5 months ago1
Are the vector registers required to have a consistent state at reset?
Closed 6 months ago4
Add clarification regarding supported index value of indexed load/stores
Closed 6 months ago1
The behavior of slideup/slidedown when i is 0
Closed 6 months ago4
vmv.s.x/vfmv.s.f behavior question
Closed 7 months ago2
Is vxsat raised based on pre-round or post-route result for vnclip?
Closed 7 months ago3
Question about '... traps on ... instructions are always reported with a vstart of 0 ...'
Closed 7 months ago11
Rounding increment is unclear when d equals to 0
Updated 7 months ago3
Signed averaging addition through vaadd
Updated 7 months ago3
Question about the vl when using element groups.
Closed 8 months ago4
Should I unroll the loop in implementation of vvadd?
Closed 8 months ago14
load mask with immediate value
Updated 9 months ago1
Main README dead link
Closed 9 months ago3
Question about vsrl instruction in RVV spec
Closed 9 months ago11
benchmarks for RVV
Updated 9 months ago2
vstart and precise abort for chaining case
Updated 9 months ago3
Note: conflict with subword (byte) AMO
Closed 10 months ago1
[Question] Possibility of some math API like i/l/llrint Vectorization
Closed 10 months ago5
Propose a PF/AF optional subset for long-vector implmentation
Updated 10 months ago3
Rotate and shift vector mask bits
Closed 10 months ago2
pdf is probably too big (uncompressed)
Updated a year ago
Issue in Constraints on Setting vl
Closed a year ago4
What does "PoR" mean?
Closed a year ago2
is vsetdcfg deprecated?
Closed a year ago2
Checks ordering: nop vs trap
Updated a year ago
Post-Ratification Clarification: Dependency from `Zve32x` to `Zicsr`
Closed a year ago5
When the value of vstart written through the csr instruction is greater than the vlmax under the current configuration, whether the hardware can be treated as an illegal instruction to implement
Closed a year ago4
If vtype.vill=1, is VLMAX equal to 0? If vlamx=0, then any value configured for vstart is treated as an illegal instruction, because in this case, any vstart value is greater than the element index.
Updated a year ago1
When vstart is not 0, is the execution of the vset{i}vl{i} command handled according to the illegal command exception?
Closed a year ago3
[question] Does V extension implies F and D?
Updated a year ago4
What happens if VLMAX ends up less than 1?
Updated a year ago2
vsetvli/vsetivli encoding
Closed a year ago2
Compares effectively AND in the mask under a mask-undisturbed policy
Closed a year ago5
Question about Narrowing Floating-Point/Integer Type-Convert Instructions
Closed a year ago2
Behavior of masked fault-only-first loads
Closed a year ago4
Question about min/max floating point reduction and NaNs
Updated a year ago6
question about setting vl
Closed a year ago4
Is vmsbc exactly the same as vmsltu with vm=1?
Updated a year ago2
Provided vdecompress example may not work with SEW=8, VLMAX>256
Updated a year ago
Is NF=1 for segment load/store banned?
Closed a year ago2
There is no chapter and section bookmark in PDF
Updated a year ago
About EXT_ZVFH
Updated a year ago2
Question about setting spike
Closed a year ago2
problem in A.4. Conditional code example
Closed a year ago1