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Jzone315's starred repositories

30-Days-Of-Python

30 days of Python programming challenge is a step-by-step guide to learn the Python programming language in 30 days. This challenge may take more than100 days, follow your own pace. These videos may help too: https://www.youtube.com/channel/UC7PNRuno1rzYPb1xLa4yktw

Language:Python42520 813 152

my-tv

我的电视电视直播软件，安装即可使用

Language:CApache-2.030100 212 900

dperf

dperf is a 100Gbps network load tester.

Language:CApache-2.05034 45 275

litex

Build your hardware, easily!

Language:CNOASSERTION2992 97 825

Free-Web-Books

Learn books from TCP/IP | HTTP(s) | HTML、CSS、JS、JQuery | Vue | PHP | Web | Web Server

Language:JavaScript931 27 1

onload

OpenOnload high performance user-level network stack

Language:CNOASSERTION575 39 162

wb2axip

Bus bridges and other odds and ends

Language:Verilog485 31 52

triSYCL

Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group

Language:C++NOASSERTION438 46 169

heterocl

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

Language:PythonApache-2.0325 17 225

pollnet

A collection of non-blocking(polling) network libs for Linux, also support solarflare APIs(Tcpdirect/Efvi)

Language:C++MIT212 14 17

exanic-software

ExaNIC drivers, utilities and development libraries

Language:CNOASSERTION144 33 62

FpgaNIC

FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs

Language:TeX118 3 1

RecoNIC

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

Language:SystemVerilogMIT103 5 21

fpga-partial-reconfig

Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

Language:SystemVerilogMIT87 27 3

HDLGen

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Language:Verilog86 7 2

core_sdram_axi4

SDRAM controller with AXI4 interface

Language:C++GPL-3.078 6 4

AccelTCP

A user-level TCP/IP stack with NIC offload of stateful TCP operations

Language:CNOASSERTION68 9 2

FlowBlaze

FlowBlaze: Stateful Packet Processing in Hardware

Language:VHDL66 6 1

hXDP-Artifacts

Language:Python57 6 3

ethernet-switch

Ethernet switch implementation written in Verilog

Language:Python40 60

NeoMem-MICRO-2024

The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering

27 10

AlveoLink

This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multiple Alveo cards.

Language:VerilogMIT19 4 1