ZipCPU / wb2axip

Bus bridges and other odds and ends

ZipCPU/wb2axip Issues

AXILUPSZ has the wrong shift for WSTRB
Updated 5 months ago
variable 'M_AXIS_TDATA' should not be used in output port connection axivfifo.v":792
Updated 5 months ago1
wbxbar slave-side STB remains asserted beyond ACK for one clock cycle for single word transaction.
Closed 7 months ago10
fusesoc file based on CAPI 1 standard.
Updated 7 months ago2
something went wrong (I guess : the version of tools)
Closed 7 months ago1
Arbitration Behaviour of axixbar
Closed 8 months ago4
the patreon support
Closed 8 months ago2
Why does the axixclk module has no wid input/output?
Closed 8 months ago2
is the axiclk can be used in the axi lite scenario
Closed 8 months ago4
axisafety.v in ZYNQ Ultrascale+ works for read operations, but not for write operations
Closed 2 years ago11
axim2wbsp.v: has different data endianness for write and read channels
Closed 2 years ago1
Whether the situation crossing 4K boundary has been handled in AXIDMA？
Closed 2 years ago2
Question regarding AW / W channel dependencies
Closed 2 years ago8
Missing LICENSE file
Closed 2 years ago3
File 'faxi_valaddr.v' is missing
Closed 2 years ago1
Is the OPT_NONESEL option currently the same as the multiple slaves?
Updated 2 years ago1
Enhacement: Sync only on TLAST option for axis2mm
Closed 2 years ago10
`default_nettype none breaks vivado global synthesis
Closed 2 years ago10
Vivado Block design, local param, and axixbar
Closed 2 years ago2
Possible enhancement: add AWCACHE parameter to axis2mm
Closed 2 years ago2
Kicking off a transfer with AXIS2MM
Closed 2 years ago16
AXIS2MM & WUSER bits/byte causes critical warning in Vivado
Closed 2 years ago3
Eliminate Ports S_AXI_C* Until Supported by AutoFPGA
Closed 3 years ago4
axi2axilite
Closed 3 years ago3
skid buffer proved by smtbmc but fail by abc pdr
Closed 3 years ago3
`s2mm` doesn't update address or len external registers
Closed 3 years ago2
Which yosys version should I use?
Closed 3 years ago2
illegal localparam in list of parameters
Closed 3 years ago2
Icarus-verilog elaboration failed in axixbar.v
Closed 3 years ago1
always block with constant assignment
Closed 3 years ago3
Syntax error in axidma.v
Closed 3 years ago1
axisafety module fails tests with ZYNQ + AXI BRAM controller
Closed 4 years ago7
aximwr2wbsp increments address too early, first data written to the next incremented address
Closed 4 years ago4
axi2axilite missing DW on axi_addr instances
Closed 4 years ago1
missing src/spec.tex
Closed 4 years ago3
Missing doc file lgpl-3.0.pdf?
Closed 4 years ago2
Wrong AXI-Stream port names in aximm2s.v
Closed 4 years ago1
Regarding err_state in WB to AXI 4 Lite Bridge
Closed 4 years ago4
High throughput AXI full master.
Closed 5 years ago1
xlnxdemo formal verification fails
Closed 5 years ago3
`default_nettype none causes issues when integrating with Xilinx IP
Closed 5 years ago5
Several files use the $clog2 function, which is not supported by Xilinx synthesis (at least 2016.4)
Closed 5 years ago1
axi2axilite.v: M_AXI_BVALID does not propagate to S_AXI_BVALID
Closed 5 years ago9
demofull incorrect read address generation in some scenarios.
Closed 5 years ago2
Explicit net type deceleration needed in axilrd2wbsp.v
Closed 5 years ago1
axi_addr.v has a double semicolon on line 180
Closed 5 years ago1
compilation error in axi2axilite.v
Closed 5 years ago1
axilrd2wbsp.v does not define err_state
Closed 5 years ago1
axilwr2wbsp.v does not define err_state
Closed 5 years ago1
`default_nettype none
Closed 6 years ago1