ultraembedded / core_sdram_axi4

SDRAM controller with AXI4 interface

ultraembedded/core_sdram_axi4 Issues

166MHz operation
Updated a year ago
VCD files are not generated
Closed a year ago
port mapping the top module with AXI ip
Closed 4 years ago8
some error has disppear when run tb/make
Closed 5 years ago1