GabbedT

os-tutorial

How to create an OS from scratch

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

computer-graphics-from-scratch

Text, diagrams, and source code for the book Computer Graphics from scratch.

MinecraftHDL

A Verilog synthesis flow for Minecraft redstone circuits

klayout

KLayout Main Sources

OpenSTA

OpenSTA engine

cacti

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

NaxRiscv

hammer

Hammer: Highly Agile Masks Made Effortlessly from RTL

mflowgen

mflowgen -- A Modular ASIC/FPGA Flow Generator

qflow

Qflow full end-to-end digital synthesis flow for ASIC designs

freepdk-45nm

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

Physical-Design

Physical Design Flow from RTL to GDS using Opensource tools.

ethernet_10ge_mac_SV_tb

SystemVerilog testbench for an Ethernet 10GE MAC core

vcd-samples

sample VCD files

Xosera

Xark's Open Source Embedded Retro Adapter - FPGA based video for rosco_m68k and others

UHDM-integration-tests

ApogeoRV

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

Advanced-Physical-Design-Using-OpenLANE-Sky130

This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

FIFO

FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.

UART-Controller

UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.

Arithmetic-Circuits

This repository contains different modules which execute arithmetic operations.

assertions-project-slathar

memorycontroller-slathar

router-slathar

usb-controller

OpenRAM_Sky130PDK_multiport

Adapted code to generate multiported SRAMs in Skywater 130 PDK