StefanSchippers / xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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Language:C 72.6%Language:Tcl 14.0%Language:Awk 7.3%Language:Roff 2.2%Language:Shell 2.0%Language:Yacc 0.6%Language:VHDL 0.4%Language:Lex 0.4%Language:Makefile 0.4%Language:Batchfile 0.0%Language:CMake 0.0%