GabbedT

Gabriele Tripi's repositories

ApogeoRV

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

Language:SystemVerilogMIT13 10

Arithmetic-Circuits

This repository contains different modules which execute arithmetic operations.

Language:SystemVerilogMIT4 10

FIFO

FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.

Language:SystemVerilogMIT4 10

UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.

Language:SystemVerilogMIT4 10

GabbedT

Informations

010

ISW_AA22-23

Main repository of the group project for the class: Software Engineering. Project members: Gabriele Tripi, Andrea Raineri, Salvatore Lo Piccolo

Language:JavaApache-2.0000

riscv-isa-manual

RISC-V Instruction Set Manual

Language:TeXCC-BY-4.0000

ZenithSoC

General purpose FPGA based System On Chip built around a powerful RISC-V 32 bit CPU.

Language:SystemVerilog000