Deadline-Design / VHDL

VHDL repository that hopefully is of broad use

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VHDL

VHDL repository.

Some design elements in the repository tilt towards being Xilinx centric. That is they utilize specific features within Xilinx FPGAs that are inferrable. When tilting towards a specific vendor(s), eg. Xilinx, mention of the vendor(s) is so made in multiple places. Conversely, when a design unit is not vendor centric, that is to say it is generally supported by all major vendors, mention of 'Any Vendor' is so made in multiple places.

Sub-directory structure hopefully is intuitive.

The focus is on inferrability, plus incorporating use of GENERICs to give some degree of flexibility.

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VHDL repository that hopefully is of broad use

License:MIT License


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Language:VHDL 100.0%