努力养家的于好看's starred repositories
Wireline-Simulink
Basic Simulink Blocks for modeling CDRs and PLLs
ClashX-V2Ray-TopFreeProxy
Top free VPN (ClashX & V2Ray proxy) with subscription links. [免费VPN、免费梯子、免费科学上网、免费订阅链接、免费节点、精选、ClashX & V2Ray 教程]
ucdart.github.io
Website for the Davis Advanced RF Technologies (DART) Lab
Digital-Calibration-of-SAR-ADC
Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)
adpll-vhdl
All-Digital Phase-Locked Loops (ADPLL) code in High Speed Integrated Circuit Hardware Description Language (VHDL) for a Field Programmable Gate Array (FPGA). The code is for the Intel/Altera Cyclone V FPGA.
MIMO-OFDM-Wireless-Communications-with-MATLAB
MATLAB Code for MIMO-OFDM Wireless Communications with MATLAB | MIMO-OFDM无线通信技术及MATLAB实现
zotero-actions-tags
Customize your Zotero workflow.
zotero-pdf-translate
Translate PDF, EPub, webpage, metadata, annotations, notes to the target language. Support 20+ translate services.
Mixed-signal-Two-Step-Flash-ADC
This circuit is a part of Mixed Signal SOC design.
SKY130_CT-DSM
A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the front-end Gm-cell and a mixed-signal simulation w/ Ngspice.
HW-Formal-Paper
Recent papers related to hardware formal verification.
USTC-Course
:heart:**科学技术大学课程资源
OpenSERDES
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
Layout-Design-of-an-8x8-SRAM-array
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.
Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Delta-Sigma-Modulator
Delta-Sigma modulator (DSM) for fractional phase locked loop.
Phase-locked-loop-IC-design
VSD workshop - Phase Locked Loop(PLL) IC Design
Book-on-gm-ID-design
Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"
Book-on-MOS-stages
Book repository "Analysis and Design of Elementary MOS Amplifier Stages"
ADC-survey
ADC Performance Survey 1997-2023 (ISSCC & VLSI Circuit Symposium)