bmurmann / ADC-survey

ADC Performance Survey 1997-2023 (ISSCC & VLSI Circuit Symposium)

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ADC Performance Survey

Data collection from the ISSCC & VLSI Circuit Symposium, 1997-2023

For use in publications and presentations please cite as follows:
B. Murmann, "ADC Performance Survey 1997-2023," [Online]. Available: https://github.com/bmurmann/ADC-survey.

@misc{adc_survey,
   author = {Murmann, Boris},
   title = {{ADC Performance Survey 1997-2023}},
   note = {[Online]. Available: \url{https://github.com/bmurmann/ADC-survey}}
}

Related Material

  • B. Murmann, "Introduction to ADCs/DACs: Metrics, Topologies, Trade Space, and Applications," ISSCC Short Course Presentation, Feb. 2022. PDF
  • B. Murmann, M. Verhelst, and Y. Manoli, “Analog-to-Information Conversion,” in NANO-CHIPS 2030, by B. Murmann and B. Hoefflinger (eds.), Springer, 2020. DOI
  • B. Murmann, “The successive approximation register ADC: a versatile building block for ultra-low-power to ultra-high-speed applications,” in IEEE Communications Magazine, vol. 54, no. 4, pp. 78-83, Apr. 2016. DOI
  • M. Keller, B. Murmann, and Y. Manoli, “Analog-Digital Interfaces—Review and Current Trends,” in CHIPS 2020 VOL. 2, by B. Hoefflinger (ed.), Springer, 2016. DOI
  • B. Murmann, “The Race for the Extra Decibel: A Brief Review of Current ADC Performance Trajectories,” IEEE Solid-State Circuits Magazine, vol. 7, no. 3, pp. 58-66, 2015. DOI
  • B. Murmann, "A/D Converter Figures of Merit and Performance Trends," ISSCCx: Circuit and System Insights, Feb. 2015. YouTube
  • B. Murmann, “Digitally Assisted Data Converter Design,” (Keynote Paper) Proc. ESSCIRC, Bucharest, Romania, Sep. 2013, pp. 24-31. DOI
  • B. Murmann, “Energy limits in A/D converters,” (Keynote Paper) IEEE Faible Tension Faible Consommation (FTFC), Paris, France, Jun. 2013. DOI
  • M. Verhelst and B. Murmann, “Area scaling analysis of CMOS ADCs,” Electronics Letters, vol. 48, no. 6, pp. 314-315, Mar. 15 2012. DOI
  • B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2008, pp. 105-112. DOI
  • B. Murmann, “Limits on ADC Power Dissipation,” in Analog Circuit Design, by M. Steyaert, A.H.M. Roermund, J.H. van Huijsing (eds.), Springer, 2006. DOI

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ADC Performance Survey 1997-2023 (ISSCC & VLSI Circuit Symposium)

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