AleksandarLilic / ama-riscv-perfsim

Cycle Accurate C++ performance model of the ama-riscv core

RISC-V Core Cycle Accurate model

Overview

Description:
Cycle Accurate C++ implementation of RISC-V RV32I ISA
Based on ama-riscv Verilog simulator

Use-cases:

• Stand-alone simulator
• Performance model
• Application development environment
• Golden Model for RTL implementation through DPI or other

Status:
In development

Milestones:
Passing all RISC-V ISA tests
Vector Export for ama-riscv core and SystemVerilog testbench

Further development:
Performance, ease of use and architecture exploration capabilities comparison with Verilog simulator

Project Structure

Header files: /SW/include/
Source files: /SW/src/
Documentation: /docs/

Branches

Main - stable release: main
Documentation: doc