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AUDIY / AUDIY_Verilog_IP

Verilog IP that AUDIY originally designed.

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AUDIY_Verilog_IP

Verilog IP that AUDIY originally designed.

Code reviews are welcome!

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Verilog IP that AUDIY originally designed.

fpgaverilog

License:CERN Open Hardware Licence Version 2 - Permissive

Languages

Language:Verilog 100.0%