AUDIY

AUDIY's repositories

FPGA based PCM oversampling FIR filter.

Language:VerilogCERN-OHL-W-2.03 10

MIT1 10

Open Source PCB Files Engineered by AUDIY

Language:HTMLCC-BY-4.01 10

Verilog IP that AUDIY originally designed.

Language:VerilogCERN-OHL-P-2.01 10

A demonstration of "Automation for FPGA Development with continuoous integration and delivery" on GitHub.

Language:VerilogGPL-3.0100

DSD Stream File (*.dsf) reader library written in C.

Language:CMIT010

Device driver libraries for I2C devices with STM32f4xx.

Language:CBSD-2-Clause010

WAV File (*.wav) reader/writer library written in C.

Language:CMIT010