912465632's starred repositories
PolarDecoder
PolarDecoders implemented in Verilog. SC, SCL, CA-SCL and CA-PC-SCL are supported.
FEC-Archive-Verilog
Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code (24), 4-dimension 8-ary phase shift keying trellis coded modulation (TCM_4D_8PSK), BCH, CCSDS and recursive systematic convolutional (RSC) Turbo codes
VerilogPolarCodes
Polar coding, decoding, and testing
ChannelCodingProjectList
List of open source channel coding projects and libraries.
Design-of-reduced-latency-and-increased-throughput-Polar-Decoder
The projects consists of the design and testbench files of polar decoder. The design is based on the research paper published on Signal Processing for communications Symposium 2012
CampusShame
互联网仍有记忆！那些曾经在校招过程中毁过口头offer、意向书、三方的公司！纵然人微言轻，也想尽绵薄之力！
verilog-axis
Verilog AXI stream components for FPGA implementation
dsp_xilinx_ip
Some basic DSP algorithms implemented with xilinx IP cores with explanation, Verilog testbenches and modelling in Python
axis_passthrough_monitor
An axis monitor ip for width, height and framerate
vivado-ip-cores
IP Cores that can be used within Vivado
AXI_DMA_FIFO
Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA
Hardware-Implementation-of-Polar-Code-for-5G-Application-on-FPGA
Polar codes are error correction codes developed by Erdal Arikan which achieves channel capacity and its reduced complexity makes it more attractive and successful. The discovery of polar code is standing as a milestone in coding theory and lot of researches are carrying out on this topic. Varieties of schemes have been proposed over these years for the generation, encoding and decoding of polar codes. The important area of research is the encoder and decoder section and most widely used one is successive cancellation decoder. Reduced complexity is the most attractive feature with an overall encoding and decoding complexity of O (NlogN) for a block size of N, which leads to its great success. Polar code concept is used in the most promising 5G technology. In this project a complete implementation of the polar Encoder and decoder is discussed with its MATLAB and Verilog implementations.
FPGA-Wireless-communication-blocks
Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS
2022_CVSD_Final
Polar Decoder
Polar-Codes-Hardware-VHDL
Polar Codes Implementation on Vhdl