The projects consists of the design and testbench files of polar decoder. The design is based on the research paper published on Signal Processing for communications Symposium 2012. The research paper name is "Reduced-Latency SC Polar Decoder Architecture" written by chuan zhang, Bo Yuan, and keshab K. parhi.
POLAR DECODER IMPLEMEMENTATION:
The algorithm for this polar decoder is similar to the butterfly diagram of the FFT (fast fourier transforms). The same is shwon in the fig. 1.
Fig.1 - decoding process of polar codes with length N = 8
It is clear from the above diagram that there are two processing elements pe1(white) and pe2(grey). The basic building block and hardware architecture of the pe1 are shown in fig.2 and fig. 3 respectively. It consists of only full adder & subtractor and half adder & subtractor.
Fig.2 - Basic Building Block of the pe1
Fig.3 - Hardware architecture of the pe1
The corresponding schematic obtained from the xilinx vivado is attached in the fig. 4. I have used structural modelling to achieve the required architecture. [Note: The block diagram in the paper takes the inputs from right side and gives the ouputs through left side. but in the schematic it is reversed. Applicable for all the following figures]
Fig.4 - Schematic of the pe1 using Xilinx Vivado
The pe2 uses the min-sum approach and its hardware architecture is shown in fig. 5. It consists of the two complement to sign magnitude conversion, sign magnitude to two cmplement conversion, EX-OR gate and comparator.
Fig.5 - Hardware architecture of the pe2
The corresponding schematic obtained from the xilinx vivado is attached in the fig. 6.
Fig.6 - Schematic of the pe2 using Xilinx Vivado
The comparator in the pe2 can be replaced with the subtractor in the pe1 and that approach is known as sub-structure sharing approach and it is used to obtain the merged pe2 element in this research paper. The merged pe2 hardware architectrue is shown in fig. 7.
Fig.7 - Hardware architecture of the merged pe1 and pe2
The corresponding schematic obtained from the xilinx vivado is attached in the fig. 8.
Fig.8 - Schematic of the merged pe1 and pe2 using Xilinx Vivado
Conclusion:
The Implementation of all the above modules are completed in the verilog HDL using the xilinx Vivado 2020.2. The verilog code and the schematic are attached with this repository.
Future works:
To implement the complete polar decoder using pipelined architecture as shown in the research paper.
Reference:
[1] Chuan Zhang, Bo Yuan, and Kesahb K. Parhi,"Reduced-latency SC Polar decoder Architectures" in IEEE ICC 2012 - Signal Processing for Communications Symposium.
Behind the scene approach to finalise this paper for the design:
The various research paper from top conferences and journals based on the polar decoder is referred and the basic understanding of the polar decoder is obtained. Then, the hardware architecture of the polar decoder is obtained from one paper [mentioned above] to implement using the verilog HDL.