absolutezero2730 / AXI_DMA_FIFO

Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA

AXI_DMA_FIFO

Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA

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Getting Start (Experiment Setup)

• Windows 7/8/8.1/10 64-bit
• Xilinx Vivado 2016/17/18.X (must include SDK)
• Board definition files for MicroZed 70X0
• USB to micro USB cable x 1
• USB to mini USB cable x 1 (for JTAG)
• RJ45 ethernet cable
• Putty.exe

System Overview

本實驗將透過AXI DMA (Direct Memory Access) 負責I/O Device與DDRX Memory之間的資料傳輸，其過程完全不需CPU(**處理器)參與，CPU只需將傳送任務 (transfer task)和敘述位址(descriptors addresses)發送給DMA代理，本身就有更多時間將運算單元與暫存器用在對其他程序的執行上。就PS端而言，典型的的傳送作業方式有兩種：

1. SG_Intr Mode
   • Definition: Transfer packets in Interrupt Mode when AXIDMA core is configured in Scatter Gather Mode.
   • 由CPU完成的作業步驟包括：初始化DMA並設立傳輸，啟用DMA的中斷系統，初始化旗標，發送封包，待發生中斷時執行程式碼迴圈(ex: 再次指定傳輸，旗標值改變)，全部傳送完畢後跳開迴圈並檢查DMA傳送結果，指定發送下一次封包或關閉DMA的中斷系統。
2. SG_Poll Mode
   • Definition: Transfer packets in Polling Mode when AXIDMA core is configured in Scatter Gather Mode.
   • 由CPU完成的作業步驟包括：初始化DMA並設立傳輸，發送封包，檢查DMA傳送結果(可能重複數次直到傳送結束)，指定發送下一次封包。

Block diagram (Compatible with the above two Modes)：

For high speed computing design, also for reducing the payload on CPU, the DMA may be the most efficient way of doing so. Why DMA? If we had data coming in from a very fast ASIC readout chip, or a multi-channel ADC device, and we need to store it very quickly through the FPGA to the DDR memory. We can't just rely on the processor to transfer data. This may overkill the intelligent performances of CPU and waste too much of its registers.

In this tutorial we are using the DMA interface to build a simple data transfer through PL to the DDR memory. The AXI DMA and AXI Data FIFO are connected through the AXIS_MM2S and AXIS_S2MM buses. These two AXIS buses mainly source and sink data stream without address. The processor will communicate through the AXI-lite bus to the DMA for setting up, initiating and monitoring. The AXI_MM2S and AXI_S2MM are memory-mapped AXI buses that connect to the memory controller.

When this experiment is complete, you will be able to:

1. Use AXI4-Stream Data FIFO and AXI DMA
2. Use the xaxidma driver on the Xilinx AXI DMA to transfer packets in polling mode
3. Use the xaxidma driver on the Xilinx AXI DMA to transfer packets in interrupt mode
4. Get DMA status through UART

Lab 1: Create a New Zynq Project

1. Launch Vivado.
2. Select File -> New Project or click on Create New Project under Quick Start.
3. Click the browse icon. Browse to set the Project location to your desired project location and click Start.
4. Set the project name to Microzed_7020_AXI_DMA_test. Also verify the Create project subdirectory check box is selected. Click Next >.
5. The project will be RTL based. Leave the radio button for RTL Project selected. Since this is a brand new project, check the box for Do not specify sources at this time. Click Next >.

6. In the Select area, select Boards.

7. Single-click the MicroZed Board that matches your configuration. Click Next >.
8. A project summary is displayed. Click Finish. The Vivado cockpit is now displayed.

Lab 2: Create and Edit a Block Design

1. The recommended way to add an embedded processor is through the Block design method via IP Integrator. Select Create Block Design.
2. Give the Block Design a name (default: design_1). Click OK.
3. In the Diagram window, click the Add IP text icon.
4. Find the ZYNQ7 Processing System IP. Either double click this or drag and drop to the Diagram window.

5. Similar to the Add IP prompt in the previous step, notice now that the Designer Assistance has provided the hint to Run Block Automation. Click the Run Block Automation link at the top of the window. (Notice the block automation wizard has identified two sources of I/O that need to be made external. One is obvious, the DDR interface. The other is labeled FIXED_IO. FIXED_IO is basically the MIO pin connections. They are labeled FIXED_IO because you cannot change their assignments in this window. The Apply Board Preset checkbox applies the Preset TCL that was included as part of the board definition archive. Leave this checked. The Cross Trigger options may be left Disabled. Click OK to connect these external signals.)
6. You will now see the Zynq block with external I/O.

7. Double click on the Zynq PS and have a look on the Block Diagram. In the Application Processor Unit, find the TTC block and simply click it.

8. MIO Configuration -> Application Processor Unit -> check the box for Timer 0. Disable it.

9. Next have a look on the Clock Configuration section. Click on the PL Fabric Clocks. We can see that we have one of the fabric clocks that has been configured as 100 MHz. We will use that clock for all of logic IPs.
10. The AXI DMA needs access to the DDR memory controller and a configuration interface to exchange information between itself and the CPU. Thus the processor will configure the AXI DMA through an AXI-lite interface and send back the AXI DMA an access for the DDR mapping. Refer to the Zynq Block Design again. For the DMA configuration, the processor requires a general purpose AXI master port so that it can configure the DMA. Navigate to the Programmable Logic area. Find the 32b GP AXI Master Ports and click it. Here we can see a general purpose master AXI interface. Now check the box for M AXI GP0 interface and enable it.

11. The other interface we need is to access the DDR controller. Go back to the Zynq Block Design section. We need to allow the DMA to read and write from the DDR. We can see from the block diagram we need to enable the High Performance AXI 32b/64b Slave Ports. So we click on that. Choose one of those. PS-PL Configuration -> HP Slave AXI Interface -> S AXI HP0 interface.

12. One more thing that we need to configure is the interrupts. In the SG_Intr Mode, the CPU will receive interrupts from the DMA. We need to enable the Fabric Interrupts. Refer to Interrupts -> Fabric Interrupts -> PL-PS Interrupt Ports -> IRQ_F2P[15:0]. Check the box and select.

13. Click OK. Now the ZYNQ7 Processing System is properly configured.

14. The 100 MHz clock should feed the two AXI interfaces. Thus we wire the fabric clock (FCLK_CLK0) to the general purpose AXI interface (M_AXI_GP0_ACLK) and the high performance slave interface (S_AXI_HP0_ACLK).

15. Click + (Add IP) to add the AXI Direct Memory Access.

16. We don't actually need the AXI streaming status (S_AXIS_STS) and the AXI streaming control ports (M_AXIS_CNTRL). Double click on the AXI Direct Memory Access to exclude these two ports, which are used in ethernet applications. Check the box for Enable Control/Status Stream. Disable it.

17. Click on Run Connection Automation. Enable the All Automation box. If we click it one by one, first for the S_AXI_LITE, we can see it wants to connect the AXI lite interface to the processor’s general purpose AXI master ports with a bridge IP named the AXI Interconnect. Second for the S_AXI_HP0, the high performance slave AXI interface of the PS, vivado wants to connected it to the DMA's scatter-gather AXI master interface (M_AXI_SG) with an AXI SmartConnect IP.

18. Click OK to run connection automation. Make sure that the general propose AXI master ports are well connected through the AXI Interconnect to the AXI lite interface of the DMA. This is for the DMA configuration. And also the scatter-gather AXI master interface is connected through the AXI SmartConnect to the high performance slave AXI interface, which is basically an access to the DDR memory.

19. Click on Run Connection Automation again to wire the last two AXI master interfaces. Enable the All Automation box. The AXI memory-mapped to stream Master (MM2S Memory Map Read Interface Signals), and the AXI stream to memory-mapped master (S2MM Memory Map Write Interface Signals) will thus be integrated through the AXI SmartConnect to the high performance slave AXI interface with the former mentioned scatter-gather AXI master interface. Click OK to run connections.

20. Click + (Add IP) to add the AXI4-Stream Data FIFO. Connect the AXI streaming master interface (M_AXIS) to the AXI streaming slave interface (S_AXIS_S2MM) of the DMA. Then connect the AXI streaming master interface (M_AXIS_MM2S) of the DMA to the AXI streaming slave interface (S_AXIS) of the FIFO. Then manually connect the clock (s_axis_aclk) and reset (s_axis_aresetn) to the fabric clock (FCLK_CLK0) and the peripheral_aresetn[0:0] of the Processor System Reset IP.

21. Click Optimize Routing to make these wires look better. Last, the two interrupts of the DMA need to be connected to the processor's IRQ_F2P. The way to do that is to use a Concat IP. Simply click + (Add IP) to add it into our Diagram. Manually connect the mm2s_introut and s2mm_introut to the In0[0:0] and In1[0:0]. Connect the dout[1:0] to the IRQ_F2P. All things are done now.

22. Click the Save button to save the block design and click the Validate Design button to make sure that we haven't make any mistake or mis-connect to these IP cores. We can safely ignore the warning messages (probably due to the some versions of board definition file...) after validating. Click the Validate Design button to make sure twice. Click OK to close the message window.

23. Save the design again. Generate the HDL Wrapper by clicking Source -> design_1 (design_1.bd) -> right click -> Create HDL Wrapper. Let Vivado manage wrapper and auto-update. Click OK.

24. Navigate to the bottom of Flow Navigator. Click and run the Generate Bitstream. This may take a while.
25. In the Vivado tool, select File -> Export -> Export Hardware. Check the box to Include bitstream. Click OK to export hardware.

Lab 3: Export Hardware Platform to SDK

1. Now to launch SDK, select File -> Launch SDK. Click OK.
2. Now being in SDK we want to create an application. Start by clicking File -> New -> Application Project.

3. Type a name for the application. Click Next.

4. On the templates page, select the Empty Application template and click Finish.

5. From the Project Explorer, open the dma_test/src folder. Then open a File Manager (開啟檔案總管). A DMA Poll_Mode example code can be found here: C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v9_3\examples\xaxidma_example_sg_poll.c. Drag the file from the file manager to the dma/src folder directly. (直接將檔案橫拉進SDK Project Explorer中的dma_test/src裡) On the appeared window, select Copy files and click OK. The file has now been copied to the src folder.
6. Set the Boot Mode jumpers to Cascaded JTAG Mode (MicroZed: MIO[5:2] = GND. Set JP3, JP2, and JP1 to positions 1-2). Connect the UART (micro-USB) to your PC. Connect a Platform Cable or Digilent Programming cable from your PC to the 2x7 JTAG socket.
7. Go back to the xilinx SDK. select Xilinx -> Program FPGA. Make sure that the connection is good. Then click Program.
8. After the FPGA programing is complete. We launch Putty.exe. On the session template, set the connection type to serial. Then refer to the serial template, select a serial line (ex: COM3). Note: you can open your device manager to confirm this. Set the Speed (baud rate) to 115200, Data bits 8 and stop bits 1, Parity None. Click Open.

Lab 4: Run DMA Poll Mode Application

1. To run the test, click on dma_test application in the Project Explorer. Then click on run configurations (Run -> Run Configuration) from the menu bar.
2. Double click on the Xilinx C/C++ Application (System Debugger). And we can then click Run. It runs the software application on the processor.

3. After the application is executed, we can look out for the results from the Putty window.

--- Entering main() ---
Successfully ran AXI DMA SG Polling Example
--- Exiting main() ---

Lab 5: Run DMA Interrupt Mode Application

1. Left the Putty terminal being opened, now click File -> New -> Application Project.
2. Type a name for the application (dma_intr_test). Click Next.
3. On the templates page, select the Empty Application template and click Finish.
4. From the Project Explorer, open the dma_intr_test/src folder. Then open a File Manager. A DMA Interrupt_Mode example code can be found here: C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v9_3\examples\xaxidma_example_sg_intr.c. Drag the file from the file manager to the dma/src folder directly. Then, on the appeared window, again, select Copy files and click OK. The file has now been copied to the src folder.
5. Right click the dma_intr_test application in the Project Explorer and refresh it.
6. Click on dma_intr_test application in the Project Explorer. Then click on run configurations (Run -> Run Configuration) from the menu bar again.
7. Double click on the Xilinx C/C++ Application (System Debugger). And we can then click Run. It runs the software application on the processor.
8. After the application is executed, we can look out for the results from the Putty window.

--- Entering main() ---
Successfully ran AXI DMA SG interrupt Example
--- Exiting main() ---