Tingyuan LIANG (zslwyuan)

zslwyuan

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Company:HKUST

Location:Hong Kong

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Tingyuan LIANG's repositories

google-ngrams-2020updated

Python scripts updated in 2020 for retrieving CSV data from the Google Ngram Viewer and plotting it in XKCD style. The Python script for retrieving ngram data was originally modified from the script at www.culturomics.org.

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google-ngrams

Python scripts for retrieving CSV data from the Google Ngram Viewer and plotting it in XKCD style. The Python script for retrieving ngram data was originally modified from the script at www.culturomics.org.

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HLS

Vitis HLS LLVM source code and examples

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bsg_manycore

Tile based architecture designed for computing efficiency, scalability and generality

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cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

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LLVM-9-for-Light-HLS

LLVM-9 with arbitrary precision integer patch for Light-HLS

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OpenCGRA

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

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Parallel-Computing-Tutorials-OMP-MPI-CUDA

These are the implementations of the previous assignments from the course COMP 5212 Parallel Computing. Various solutions have been tried and current source codes are based on those get the highest performance on the server. These source codes cover the range from OpenMP, MPI to CUDA. The assignments are required to solve the shortest path problem and Bellman-ford algorithm has been involved, considering that there could be negative circles in the graph. Thanks to Prof. LUO's detailed lectures and TAs' patient guide.

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Verilog-UART

3个独立组件:UART接收器、UART发送器、UART交互式调试器

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abc

ABC: System for Sequential Logic Synthesis and Formal Verification

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AutoBridge

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

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biteopt

Derivative-Free Optimization Method

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circt

Circuit IR Compilers and Tools

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cloc-action

GitHub Action to Count Lines of Code with https://github.com/AlDanial/cloc

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DSS

DASS HLS Compiler

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kahypar

KaHyPar (Karlsruhe Hypergraph Partitioning) is a multilevel hypergraph partitioning framework providing direct k-way and recursive bisection based partitioning algorithms that compute solutions of very high quality.

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NoCpad

HLS for Networks-on-Chip

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NUCPU

A toy CPU

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openpiton

The OpenPiton Platform

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Python-Email-Sender

This project shows the details of send a email via Python with attachment. All the details are wrapped in a function. Therefore, usually, user can only care about how to send emails according to the lists with the simple function. This email sender is based on Python 3.6.

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RapidLayout

RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms

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RapidWright

Build Customized FPGA Implementations for Vivado

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riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

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riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

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rsd

RSD: RISC-V Out-of-Order Superscalar Processor

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sky130-hello-world

Minimal SKY130 example with self-checking LVS, DRC, and PEX

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stencil_hls

Implementation of time and space-tiled stencil in Vivado HLS.

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T13x

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

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vericert

A formally verified high-level synthesis tool based on CompCert and written in Coq.

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vsdstdcelldesign

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.

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