zhongyuchen / mips-32bit

Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board

mips-32bit

• Four versions of MIPS 32bit implemented with Verilog HDL in Vivado HLx.
• For each version of MIPS, there are several interesting test programs in both assembly and hex code that solve problems such as Fibonacci (recursion), Hanoi tower, select sort and so on.
• Simulation files are also implemented.
• All versions can be used on Digilent Nexys4 DDR Board and all variables in the CPU are visible on the development board!
• Each version came with a detailed report (in Chinese) explaining the design and result.
• Related materials and course slides are also provided!

MIPS 32bit

The following versions of MIPS 32bit are included:

• monocycle
• multicycle
• pipeline
• pipeline with cache
  • one instruction cache and one data cache

Prerequisites

• Install Vivado
• A Digilent Nexys4 DDR Board

Usage

Preparations

• In module imem(), there is this line of code for loading hex instructions. Replace <FILE> with the actual path of the hex program

$readmemh("<FILE>", RAM);

• In module regfile(), there may be this line of code for resetting the register. Replace <FILE> with the actual path of emptyreg.dat

$readmemh("<FILE>",rf);

• When writing file path, use / instead of default \ !

Run

• Simulation:
  • just run Simulation
• Nexys4 DDR Board:
  • run Synthesis
  • run Implementation
  • run Generate Bitstream
  • open Hardware Manager
  • connect the board

Links

• MIPS simulator QtSpim can run MIPS assembly (32 bit)
• MIPS Converter converts MIPS assembly into hex code and vice versa