zhanghongce

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

egg

egg is a flexible, high-performance e-graph library

common_cells

Common SystemVerilog components

kissat

mockturtle

C++ logic network library

wal

WAL enables programmable waveform analysis.

LLVM-9.0-Learner-Tutorial

A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.

hw-cbmc

The HW-CBMC and EBMC Model Checkers for Verilog

Gamora

Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)

LLMs-for-EDA-Tutorial

asl-interpreter

Example implementation of Arm's Architecture Specification Language (ASL)

cbmc-viewer

CBMC Viewer scans the output of CBMC and produces a browsable summary of its findings, making it easy to root cause the issues it finds.

ic3po

IC3PO: IC3 for Proving Protocol Properties

RTL-Timer

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization

btor2mlir

BTOR2 MLIR project

calyx-riscv

RISCV Core written in Calyx

CHA

super-prove-build

divider

Hardware Division Units

chisel-formal-verification

Formal verification tools for Chisel and RISC-V

wasim-cpp

bitwuzla-sys

Low-level Rust bindings for the Bitwuzla SMT solver

wordEc

EDA4SAT

rIC3

A high-performance IC3/PDR algorithm implementation in Rust.

DAC24

Predicting Lemmas in Generalization of IC3 (Accepted by DAC2024)

Divider

Hardware integer divider module

fudian

Open source high performance IEEE-754 floating unit

FTEC-5320-sp2024-student

MachSuite