ygot's starred repositories
secretflow
A unified framework for privacy-preserving data analysis and machine learning
pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
Spike-Driven-Transformer
Offical implementation of "Spike-driven Transformer" (NeurIPS2023)
frame-codebase
The complete codebase for Frame
Xilinx_Library
Vivado诸多IP,包括图像处理等
Spike-Driven-Transformer-V2
Offical implementation of "Spike-driven Transformer V2: Meta Spiking Neural Network Architecture Inspiring the Design of Next-generation Neuromorphic Chips" (ICLR2024)
wav-lpddr-hw
Wavious DDR (WDDR) Physical interface (PHY) Hardware
DDR2_Controller
DDR2 memory controller written in Verilog
Get_Moving_With_Alveo
For publishing the source for UG1352 "Get Moving with Alveo"
lpddr4-test-board
Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM
neuromorphics-daily-arxiv
Neuromorphic paper list, automatically updating everyday at 8:00 am GMT.
RISC5Verilog_lpddr
RISC5Verilog for Pipistrello using lpddr memory
dpu_kmeans
Implementation of the K-means algorithm on UPMEM PIM architecture
SNN-for-Finger-Velocity-iBMI
An Energy-Efficient Spiking Neural Network for Finger Velocity Decoding for Implantable Brain-Machine Interface
snn-cvt-dual-phase
Towards Optimal Conversion from ANNs to SNNs with Dual-Phase Optimization, TNNLS, 2023