vsandeepsekhar

uvm_all_wr_rd

UVM register sequence to write all registers and read back with fix pattern

NoobsCpu-8bit

A simple 8bit CPU.

python-svlog

Verilog development framework with DPI-python verification utils

wbi2c

Wishbone controlled I2C controllers

data-scientist-roadmap

Toturials coming with the "data science roadmap" picture.

awesome-datascience

:memo: An awesome Data Science repository to learn and apply for real world problems.

coding-interview-university

A complete computer science study plan to become a software engineer.

SystemVerilogReference

training labs and examples

UVMReference

Reference examples and short projects using UVM Methodology

tbengy

Python Tool for UVM Testbench Generation

Data-Structure-Algorithm-Programs

This Repo consists of Data structures and Algorithms

uvm-testbench-tutorial-simple-adder

A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology

verilog-ethernet

Verilog Ethernet components for FPGA implementation

corundum

Open source FPGA-based NIC and platform for in-network compute

100DaysofDSAlgo

riscv_workshop_collaterals

This repository is created for conducting RISC-V 5-day workshops