How to run ---------- This Makefile is made to be used with Synopsys VCS but it should be easily adaptable to any SystemVerilog simulator. To run the simulation you just need to type: $ make -f Makefile.vcs Configuration ------------- You'll need to edit the Makefile.vcs file and change the variable 'UVM_HOME' to your UVM installation. Explanation of the code ----------------------- An explanation of this UVM testbench can be found at: http://colorlesscube.com/uvm-guide-for-beginners/