mergefork
There are 2 repositories under mergefork topic.
DECAfpga / BrianHG-DDR3-Controller
DDR3 Controller, 16 read, 16 write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included. [This fork is only a mirror, not for development]
Language:SystemVerilog 3BBC micro - Demistified for Deca & Neptuno. [This fork is only a mirror, not for development]
Language:VHDL 1- Language:Assembly 1
Dual 32 MB SDRAM + 2 MB SRAM MiSTer module with 3 extra pins for DECA retro cape 2
- Language:Verilog 1
- Language:VHDL 0
- Language:VHDL 0
sockitfpga / jtframe
MiSTer SoCkit version. Common framework for MiST(er), SiDi, ZX-UNO/DOS and Unamiga core development. With special focus on arcade cores.
Language:Verilog 0Memtest core for SoCkit board to test SDRAM MiSTer modules with GPIO addon
Language:Verilog 0- Language:SystemVerilog 0
Uses the SDRAM controller from TurboGrafx16 to give an SDRAM chip a heavy workout. Check SoCkit folder for MiSTer port.
Language:Assembly 0Acorn Archimedes core DeMiSTified, ported to TC64 and de10lite
Language:Assemblyc64 demistified core. Audio I2S on i2s branch
Language:VHDL- Language:HTML
- Language:VHDL
Flappy Bird core for MiSTer, MiST, DeMiSTify, Xilinx, GoWin, ...
Language:Verilog- Language:Verilog
- Language:VHDL
- Language:VHDL
- Language:VHDL
- Language:Verilog
- Language:VHDL
Q*Bert core for MiSTer for the Terasic/Arrow SoCKit
Language:VerilogSega System 1 for Terasic SoCKit FPGA board running MiSTer
Language:VerilogSoCkit(MiSTer) arcade core for Tecmo arcade classics: Rygar (1986), Gemini Wing (1987), and Silkworm (1988).
Language:VHDL- Language:VHDL
- Language:SystemVerilog
- Language:SystemVerilog
- Language:Verilog
Absolute beginner's guide to the de10-nano [so it should apply to SoCKit as well]
Language:Shell- Language:Verilog
Checks the sanity of the SDRAM module on MiST and MiSTer systems
Language:Verilog- Language:VHDL
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TurboGrafx-16 CD / PC Engine CD for SoCkit (MiSTer)
Language:VHDL- Language:VHDL
