DECAfpga / MiSTery

Atari ST/STe core demistyfied. See Readme in board folder (Deca, ...)

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MiSTery - An Atari ST/STe core for the MiST board

Initial Port to Turbo Chameleon 64 by Alastair M. Robinson.

Limitations of the TC64 port:

  • No TG68 (68020) - only the cycle-accurate FX68K core is supported.
  • No hard drive support yet - coming soon!

Features:

  • Cycle accurate STe GLUE+MMU combo (re-created from the original schematics)
  • Cycle accurate FX68K CPU core
  • Cycle accurate Blitter offered by Jorge Cwik
  • Mostly cycle accurate shifter based on schematics made from reverse engineering
  • MegaSTe 16 MHz CPU mode
  • Turbo bus - double RAM access speed
  • RAM size up to 14MB
  • Support for all TOS versions
  • 2 Floppy disc drives
  • ACSI hard disc support
  • Viking compatible hi-res monochrome card support
  • Real IKBD with HD63701 MCU
  • Real MIDI input/output using MiST's UART pins
  • Serial/parallel port redirect to USB
  • Gauntlet type 4 joystick interface support
  • STe controller port support
  • RP5C15 RTC Chip
  • Ethernet on cartridge port interface (Ethernec)
  • Optional scandoubled/YPbPr video output

Usage:

Put the core.rbf and the TOS as tos.img to the SD-Card. TOS/hard disc/floppy images are selectable in the OSD (F12). With F11, you can toggle between normal and STe joystick ports.

Current issues/limitations:

  • Some MFP imperfections
  • No RAM cache for Mega STe (but the cache control selects turbo bus speed)
  • Only fake LMC1992
  • PAL clock only (32.084 MHz)
  • Since Jagpads have 21 buttons, not all are mapped to MiST controllers when using STe game ports
  • No STe paddle handling (but it has 0 software support)

Thanks to:

  • Till Harbaum for the MiST board, original MiST core, new IKBD code
  • Jorge Cwik for the FX68K CPU core, FX ST Blitter code and shifter decap
  • Christian Zietz for recovering the schematics of the GSTMCU

About

Atari ST/STe core demistyfied. See Readme in board folder (Deca, ...)


Languages

Language:Assembly 52.4%Language:VHDL 22.2%Language:Verilog 20.4%Language:SystemVerilog 3.7%Language:C 1.0%Language:Shell 0.1%Language:Makefile 0.1%Language:Tcl 0.1%