Tommy Thorn's repositories
Reduceron
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
Paperlike-Raspberry-Pi-4
How to use a Dasung Paperlike HD-F, HD-FT, and Paperlike 253 with Raspberry Pi 4 [and other hosts?]
verilator-demo
A very simple example of how to use Verilator
kinesis-firmware
humble hacker firmware
OrangeCrab_Hello
Simple OrangeCrab Verilog design using LED and serial IO
riscv-opcodes
RISC-V Opcodes
riscv-plic-spec
PLIC Specification
rust-verilog-cosim
Small example of how to co-simulate a Rust model against a Verilog implementation, using Verilator
verilog-sim-bench
Verilog simulation workload extracted from Reduceron
anti80
Anti80 is design exercise in a more compiler friendly architecture in roughly the same implementation budget as the Z80
ecp5-inferred-memory
A quick little design to experiment with memory inference and timing impact
OrangeCrab
ECP5 breakout board in a feather physical format
previous-code
Full mirror of the Previous NeXT computer emulator's SVN repository http://previous.alternative-system.com (including SVN's awkward branches)
sesc-mirror
Unadulted git mirror of the SESC CVS repo on https://sourceforge.net/p/sesc/code/sesc