tommythorn / verilog-sim-bench

Verilog simulation workload extracted from Reduceron

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Verilog simulation benchmark

20200611

This design is extracted from Reduceron @0928fbd3, the KnuthBendix workload. On a Xeon E3-1275 v5 the simulation takes about 90 sec.

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Verilog simulation workload extracted from Reduceron


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Language:Verilog 99.9%Language:C++ 0.1%Language:Makefile 0.0%