stffrdhrn / sdram-controller

Verilog SDRAM memory controller

stffrdhrn/sdram-controller Issues

CPLD latch output issues
Closed 4 years ago3
rd_ready signal missing
Closed 5 years ago3
Multiple modules accessing SDRAM
Closed 5 years ago5
Some addresses are not accessable
Closed 5 years ago3
rd_enable latching (or lack of it)
Updated 6 years ago1