stffrdhrn / sdram-controller

Verilog SDRAM memory controller

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CPLD latch output issues

briansune opened this issue · comments

Just wonder, if using FPGA the modified example code from your repository seems dont have big issues due to most FPGA do have output buffer register to control the timing.

However, if considering the case of CPLD devices, most of them dont even able to have output IO register buffer to control the clock alignment.

So after some testings and findings, i discovered that CPLD device have unnecessary switching noise at the output due to some signal paths only use latches and MUXx.

Correct me if i think in the wrong direction =]

This might be true. U have not heard of anyone trying on cpld devices. You should be able to patch all outputs to be registered if that is needed.

hello sir,
i have tried to run your code, what is sdc file in it ?
how to do this ?
create_clock -period "20ns" CLOCK_50
derive_pll_clocks
derive_clock_uncertainty

Dear shubhamnrt open a new issues as this is not related to my original question. I am closing this issues as the creator had answered my issues.
Bests~