rd_ready signal missing

[Navraj Kambo]

I noticed that the test bench you've provided doesn't include the rd_ready signal, and was wondering if you could expand on how that signal goes high or low with respect to the busy signal.

[Navraj Kambo]

For my application, i'm writing and reading data to RAM between an audio codec.
Audio ADC Fifo -> SDRAM Controller + Custom Logic -> Audio DAC Fifo
I've designed a module which communicates to your SDRAM controller and the FIFOs for the Audio Codec, however I'm unsure about how the read ready signal is to be used. I've made a test bench of how I think the signals interact, and wouldn't mind your input (specifically on when the read ready signal goes high).

More information on my setup:

1. ivalid goes high
2. iready goes high (data is transferred when ivalid and iready are both high)
3. write goes high and wdata gets data
4. busy toggles
5. write goes low when busy is seen
6. waddr incremented
7. read goes high
8. busy toggles
9. read goes low when busy is seen
10. data is collected from rdata when busy is low and read ready (rdy) is high
11. raddr incremented
12. ovalid goes high and waits for oready
13. data is transferred to Audio DAC when ovalid and oready are both high

Notes

• audio samples at 48kHz stereo (96kHz actually since L channel then R channel every period)
• switch between L and R channel using clk_lr_aud (48kHz)
• have two of these custom modules feed into your ram controller, being switched by clk_lr_aud signal
• i've sped up the audio clks for the simulation
• i'm using the DE1-SoC with the Wolfson WM7831 codec and 64MB of ram

[Stafford Horne]

Hello, I have a similar project which uses my sdram-controller for audio recording.
https://github.com/stffrdhrn/digi-recorder

The rd_ready signal indicates that the read data is ready on the rd_data bus. The busy signal indicates that the controller is busy with a read or write transaction and you should not issue any commands during that time.

[Navraj Kambo]

Hey, thanks for the help! Your module works as expected and I was able to successfully implement the SDRAM controller between the codec FIFOs. I'll be posting my project here soon. Again, thanks. You are a life saver!