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sikthehedgehog
/
vdpnotes
VDP notes
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sikthehedgehog/vdpnotes Issues
FIFO flag description is wrong
Updated
in 13 hours
Comments count
1
Bug with plane B tile bank being forced to 0 when plane A bank is 0
Updated
in 13 hours
Comments count
1
Document the clocks
Updated
22 days ago
What does reg $0C bit 4 do?
Updated
a month ago
Figure out why VRAM address bit 0 is inverted
Updated
a month ago
Comments count
3
Document all the latencies
Updated
2 months ago
DMA source address register lock-up
Updated
3 months ago
How does the FIFO work?
Closed
3 months ago
Comments count
1