Bug with plane B tile bank being forced to 0 when plane A bank is 0
sikthehedgehog opened this issue · comments
According to Nemesis, plane B is forced to use the low 64KB of VRAM if plane A is also configured that way:
https://gendev.spritesmind.net/forum/viewtopic.php?p=18732&sid=8e1b4f15ba636b4f760bb9f3588038d9#p18732
Setting bit 0 of this register will rebase all layer A (and window) pattern data to begin at the upper bank of the VRAM. Bit 4 of this register only has an effect when bit 0 is set to true. Setting bit 4 to true as well will rebase all layer B pattern data to the upper VRAM bank as well.
Figure out what's going on in the VDP that causes this.
VDP seems to be sending the correct bit when setting up the address which is weird. Either there's some timing issue that isn't obvious that causes the wrong address to be read, or Nemesis made a mistake while testing back then.
May be worth having a test ROM to try on a Teradrive (or a console modded with extra VRAM).