FIFO flag description is wrong

[Sik]

The description of the FIFO full and empty flags is wrong. According to the current tidbits.md:

• FIFO FULL is set when the two indices are identical after a write, and reset when the indices stop being identical.
• FIFO EMPTY is set when the two indices are identical after flushing, and reset when the indices stop being identical.

This is wrong. It seems to be correct when the whole entry is flushed, but it doesn't work if a 16-bit write is done with an 8-bit bus: both flags get set simultaneously on the first flush (because the two indices still match). There must be one condition that's still missing.

[Sik]

Looking more carefully at the behavior:

• If the indices stop matching, both flags are reset, period.
• If the indices match and either flag is set, that flag remains set.
• If the indices match and a new entry has been inserted, FIFO is full.
• If the indices match and a pending entry has been fully flushed, FIFO is empty.

The emphasis in the last point is where the issue arises. It isn't enough for a write to go through, it explicitly checks that the index advanced to the next entry.

The part where the flags keep being set if they're already set is also not mentioned, but that may just be logic to keep the flags intact when nothing happens (since the expression replaces the whole value, instead of having separate set and reset conditions).