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shahsaumya00 / Floating-Point-Adder

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

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digital-designieee754pipeline-frameworkverilog

Floating-Point-Adder

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

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32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

digital-designieee754pipeline-frameworkverilog

License:MIT License

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Language:Verilog 100.0%