sequencer

rocket-doc

gitakc

block-inclusivecache-sifive

riscv-debug-spec-ci

wishbone

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-circt

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

chisel-testers

Provides various testers for chisel users

chisel3

Chisel 3

chiselv

A RISC-V Core (RV32I) written in Chisel HDL

cva6-wrapper

Wrapper for ETH Ariane Core

felix-infra

The entry point of Felix Universe.

fpga-shells

gecko-dev

Read-only Git mirror of the Mercurial gecko repositories at https://hg.mozilla.org. How to contribute: https://firefox-source-docs.mozilla.org/contributing/contribution_quickref.html

gemmini

Berkeley's Systolic Array Generator

ibex-wrapper

Wrapper for lowRISC Ibex

icenet

Network components (NIC, Switch) for FireBox

maltese-smt

A scala SMT library focused on arrays, bitvectors and uninterpreted functions.

musl

repo

Arch Linux CN Repository

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

riscv-boom

BOOM: Berkeley Out-of-Order Machine

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-sodor

educational microarchitectures for risc-v isa

scalehls

A scalable High-Level Synthesis framework on MLIR

sha3

sifive-blocks

Common RTL blocks used in SiFive's projects

testchipip

verilator

Verilator open-source SystemVerilog simulator and lint system