sequencer

Jiuyang Liu's repositories

arithmetic

Language:Scala30 5 3

rocket

A modern version of Rocket Core.

Language:ScalaNOASSERTION11 4 1

riscv-cosim

Language:Verilog5 50

tilelink

Language:Scala4 40

chisel-circt-binder

The Chisel Convert Phase implemented with JVM Panama

Language:Scala3 40

rocket-test

RISC-V Core Test Framework

3 40

clx

TL Serdes

Language:Scala2 40

firesim-hw

Language:Scala2 30

PLCT-Weekly

软件所PLCT实验室在开源领域的不定期简报

Language:HTMLCC-BY-SA-4.02 20

rvdecoderdb

Language:Scala2 20

berkeley-hardfloat

Language:ScalaNOASSERTION1 20

chisel-panama-standalone-plugin

Language:C++NOASSERTION1 20

firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

Language:ScalaNOASSERTION1 20

regmapper

Language:Scala1 20

t1-DRAMsim3

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

Language:C++MIT1 10

tlaurora

Language:Scala1 30

ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

Language:ScalaNOASSERTION1 10

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

Language:ScalaApache-2.0020

firesim-sw

Language:C++NOASSERTION030

firrtl-spec

The specification for the FIRRTL language

Language:TeX010

ha-core

:house_with_garden: Open source home automation that puts local control and privacy first.

Language:PythonApache-2.0000

ide-dbg

Language:Scala020

mill

Your shiny new Java/Scala build tool!

Language:ScalaMIT010

nixos-apple-silicon

Resources to install NixOS bare metal on Apple Silicon Macs

Language:NixMIT010

nixpkgs

Nix Packages collection

Language:NixMIT020

riscv-opcodes

RISC-V Opcodes

Language:PythonBSD-3-Clause010

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

Language:AssemblyCC-BY-4.0010

tsc

CHIPS Alliance Technical Steering Committee

Apache-2.0010

tvip-axi

AMBA AXI VIP

Language:SystemVerilogApache-2.0000

utils

Language:Scala020